Intel: 'EUV Facts Don't Add Up' for 22 nm in 2011
David Lammers, News Editor -- Semiconductor International, 4/22/2008 8:38:00 AM
 |
 |
| Mark Bohr, Senior Fellow, Intel |
Instead, Intel intends to extend 193 nm immersion lithography with “various techniques,” said Bohr, who directs the “pathfinding” phase of process development for the 22 nm generation. EUV may still be able to provide “a backup option or an upgrade,” but it won’t be used for first production. Listing the major technical challenges, including EUV masks, mirrors, the “high-intensity” sources, and resists, Bohr added that “all are making steady progress, but not fast enough to be ready in 2011.”
Intel is continuing to develop EUV lithography, and Bohr said one encouraging trend is that “a growing number of companies see EUV as a way to get to their 22 nm technology, or maybe 16 nm. We have got to find ways to make it work.”
Intel is working on design techniques that can be coupled with different lithography solutions, he said, noting that proprietary forms of phase-shift masks (PSMs), design for manufacturing (DFM) and optical proximity correction (OPC) developed by the lithography team have been able to extend immersion lithography to the 22 nm node.
 |
| Intel sees computational lithography extending immersion ArF lithography, while also pursuing EUV lithography. |
Although Bohr did not provide details, over the past year, Intel technologists have been discussing a form of computational lithography that involves etching pixels with various shapes and slopes on what appears to be a totally transparent, chromeless piece of glass. When 193 nm light is projected, the pixelated mask creates phase-shifted patterns that could extend immersion lithography to 22 nm.
At an Intel research review day last June, Yan Borodovsky, director of advanced lithography, presented Intel’s computational lithography approach. He said the fact that Intel has an internal mask technology operation in Santa Clara, Calif., provides it with a distinct advantage in terms of developing pixelated masks. The approach also requires significant computing resources to run the algorithms that calculate Maxwell’s equations in reverse. Borodovsky also explained the technology last September in a webcast interview with Dan Hutcheson, CEO of VLSI Research Inc. (Santa Clara, Calif.), explaining that the technique requires etching pits on the mask to create interfering light waves that correspond to the layout of the design intent. “It is very, very different,” Borodovsky said, adding that the algorithms must be able to reduce the time and computing power to make the approach practical.
 |
| A form of phase-shift mask lithography, pixelated masks require etching sloped patterns into a glass substrate to shift the phase of 193 nm light. Intel presented the technology at Developer's Forum in Santa Clara, Calif., in June 2007. |
Borodovsky also presented slides illustrating a 65 nm pixelated test mask and gave a video demonstration of the mask, using a laser pointer as the light source. One source, who declined to be identified, said for its 32 nm technology, Intel was able to use double patterning (DP) to extend immersion lithography for the critical layers, with conventional DFM techniques. At 22 nm, the source said the pixelated masks will further extend immersion without the use of extensive DP, adding that Intel believes EUV remains far too expensive for commercial production.
Bohr emphasized that Intel is sticking with its two-year cadence to introduce new technologies. In September 2007 at the Intel Developer Forum, Intel demonstrated a 32 nm test chip with 1.9 billion transistors, and a cell size of 1.82 µm2.
Now, Bohr said it is “fairly routine” to be creating 32 nm test chips at the company’s development fab in Hillsboro, and said the next public milestone will be to demonstrate working 32 nm microprocessors. One advantage, he said, is that Intel can extend its high-k/metal gate technology to the 32 nm node and beyond.
“We are on schedule to ramp 32 nm MPU products in the second half of 2009,” Bohr said. The 22 nm ramp will come in 2011, although challenges remain.
Asked whether Intel will be able to extend planar transistors to the 22 nm node, Bohr said, “Whether it is planar or vertical, these are the kinds of questions we are asking ourselves. There are a couple of paths, including planar, that look like they can work at 22 nm. But there are quite a few challenges at 22, besides the patterning challenges, to meet the performance and leakage requirements,” Bohr said.
Talkback
Related Content
Related Content
There are no other articles related to this article.
