Although 157 and even 126 nm wavelengths were once considered for future lithography generations, and it was also assumed that extreme ultraviolet (EUV) lithography would make its entrance much earlier than is now expected, it is now clear that the exposure wavelength will be stuck at 193 nm for the next several technology nodes, noted Mark Mason, director of design data integration at Texas Instruments (TI, Dallas). "That's going to put increasing pressure on masks," he said. "And in fact, over the history of resolution enhancement technology, that's essentially the way we've moved forward — by putting pressure on the mask."

For at least the past 10 years, many critical mask specifications have scaled much faster than the wafer dimensions that we think about when considering Moore's Law, according to Chris Mack, gentleman scientist (Austin, Texas). Critical dimension uniformity (CDU) of contacts and vias, for example, has been scaling ~3× faster than the wafer minimum half-pitch. "This is causing a lot of difficulties and hardships for the maskmakers, but it also is enabling these masks to continue to be used as we push down generation after generation," Mack said.

As a continuation of the themes in our September cover story on advanced photomasks, Mason and Mack — along with Luigi Capodieci, AMD Fellow, RET/OPC automation and DFM, at Advanced Micro Devices (AMD, Sunnyvale, Calif.) — gathered for a webcast later in the month to discuss advanced photomasks. In particular, they examined the rapid scaling of mask features, the growing need for design for manufacturability (DFM), and the role of double patterning at 32 and 22 nm nodes.

"The strong motivation that we have for design for manufacturability [DFM] is that for 32 and 22 nm, EUV will not be available for the next two technology nodes," Capodieci said. More aggressive optical proximity correction (OPC) and resolution enhancement techniques (RETs), as well as increasing use of double exposure schemes, have enabled photomasks to scale at an incredible rate and have also made DFM more than just a buzzword.

The march from node to node has required a transition from traditional design rules to rule-based OPC around the 130 nm node, finally to model-based OPC in the sub-100 nm set of geometries, Capodieci explained. "At this point, design for manufacturability is the summation of the design rules, the resolution enhancement that we put onto the mask, rule-based OPC, model-based OPC and the full-chip printability verification." Although this type of incremental solution has been sufficient, he said, the process variability the industry faces at 45 nm will require more.

For k₁<0.35, layout regularity will be "absolutely necessary," Capodieci said. But even this will not be sufficient at 22 nm, so a moderate use of double patterning will be necessary. There are several techniques for double patterning, ranging from a single film and single etch to two films with a single etch to two films and two etches. To maintain a simpler layout, one film and one etch would be used, but that would require chemical advancement in the form of a memoryless resist, Capodieci explained. Although a two film, two etch approach would make use of existing processes and materials, it would require the use of multiple mask sets.

1. Double patterning feasibility testing has produced shapes that were not possible with single patterning, such as very square line ends, as shown here. (Source: Texas Instruments)

TI has done some two-pattern, two-etch feasibility testing at the 45 nm node, and found some interesting features (Figure), including some that could not be achieved otherwise. "For example, the very square line-end patterns, we've never been able to get with single-mask technologies," Mason said. "That's an excellent feature of a dual mask patterning approach that allows you to push line end to line end spacing design rules and so forth."

One of the most important DFM advances needed for double patterning will be two-dimensional design rule checking, Capodieci said. AMD has integrated a new design rule methodology into its standard verification flow that it has pioneered based on pattern matching. This sort of methodology will help to restrict design rules and design regularity, which will be the fundamental enablers for manufacturability and yield, Capodieci said.

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