When Is PowerPC Not PowerPC

"When is PowerPC not PowerPC?" may seem like a silly question, but it's not. In 1995, a new 64-bit RISC processor was introduced in the AS/400. At that time, the architecture of that processor was said to be PowerPC. Actually, we said it was PowerPC-AS, but there was little or no explanation of why the "AS" was attached to the PowerPC name. Soon most people, including this author, were simply calling the architecture PowerPC.

Discussions of the iSeries in the press often state that this server uses IBM's latest generation of PowerPC chips. This has led some to speculate about the possibility of running OS/400 on another PowerPC platform. The PowerPC G4 processor used in the Apple Mac is sometimes mentioned in various press articles as a potential low-end platform for OS/400. The problem with this type of speculation is a misunderstanding of the processor architecture needed to run OS/400. You see, OS/400 does not use the PowerPC architecture, and it never has.

With the introduction of the POWER4 processors in the iSeries, there was a small attempt to correct this misunderstanding by calling the processor architecture POWER instead of PowerPC. This name change, however, still does not clarify the situation, because OS/400 does not use the POWER architecture.

If OS/400, the fundamental operating system of the iSeries, uses neither the PowerPC nor the POWER architectures, what does it use? As I shed some light on this question, I hope to also show when PowerPC is not PowerPC.

Shortly after the announcement of the AS/400 in 1988, it became clear to many of us inside the IBM Rochester development laboratory that we needed to update the processor architecture of the AS/400 in order to support the many new applications and new programming languages we expected to emerge during the 1990s. (For a discussion of what "architecture" means in this context, see "Architectures Defined," below.) Data warehousing was an example of an application we believed would be important in the future, and many of us saw object-oriented programming languages becoming an important tool for many AS/400 customers. Most of these emerging applications and languages could be described as being very compute-intensive, meaning they required fairly high-performance processors.

The original processor architecture in the AS/400 had the horrible name Internal Microprogrammed Interface (IMPI). This processor architecture was originally defined and even named by this author in the middle 1970s for the System/38. It was a very good architecture for the types of traditional business applications found in System/36 and S/38 shops in the 1980s, and so it was carried over into the early AS/400s. It was not, however, the type of processor architecture that was ideally suited for compute-intensive applications.

In early 1991, a highly talented team of people from IBM development locations in Rochester, Minnesota, and Austin, Texas, got together with their counterparts from IBM Research locations in New York to define a new processor architecture. The intent was to create a new architecture that could be used for all future models of both the AS/400 and the RS/6000. We called that architecture Amazon.

The Amazon name was selected because the code name for the first common microprocessor to be used in the AS/400 and RS/6000 was Belatrix. Note that processors can be implemented using multiple chips, or a processor can be contained on a single chip. Single-chip implementations are commonly called microprocessors. Belatrix was to be a single-chip implementation.

Belatrix is the name of a star in the constellation Orion. This star is also called the Amazon star. Belatrix was being designed in the Austin laboratory to be the star of the Amazon architecture.

We decided to define the Amazon architecture by starting with the PowerPC architecture. To the PowerPC architecture we added those unique features from both the POWER and the IMPI architectures that were necessary to support the RS/6000 and the AS/400. We then added additional features that we felt were necessary for future applications and operating systems that might run on implementations of the Amazon architecture.

The original POWER and PowerPC processor architectures were designed for use in single-user workstations (for a historical perspective, see "A Brief History of POWER and PowerPC," below). In order to use either of these architectures in a multi-user, multi-application server, many new functions had to be added. For example, neither the original POWER nor the original PowerPC architectures had support for multiprocessors.

One of the most important features that had to be added to Amazon was the support for the single-level store of the AS/400. We could not use the addressing mechanism that was originally created for POWER and later adapted for PowerPC. That addressing mechanism assumed a Unix style of addressing where each Unix process has its own private address space. The single-level store of the AS/400 assumes a shared address space for all processes. To support single-level store, we had to define a second complete addressing mechanism for Amazon.

Some additions were made to the Amazon architecture to support high-performance technical computing. The POWER processors were initially designed to support the technical computing marketplace, and many of the features that were part of the POWER architecture were not included in the more general PowerPC architecture.

In the end, we had created a brand-new IBM processor architecture. For future compatibility, Amazon would include the full PowerPC architecture, both 32- and 64-bit versions, along with all of the extensions needed for 64-bit implementations of the AS/400 and the RS/6000.

Because the Belatrix microprocessor was such an extremely ambitious undertaking, which would likely take several years to complete, the decision was made to have Rochester develop the first two processors to use the Amazon architecture. Actually, since these processors would be used only in the AS/400, these processors would implement only the parts of the Amazon architecture needed by OS/400. In other words, these first two processors (known by the code names of Muskie and Cobra) implemented only a subset of Amazon. They did not implement the full PowerPC architecture. Specifically, they did not implement any of the 32-bit PowerPC architecture.

In spite of the fact that these processors did not implement the full PowerPC architecture, they were still called PowerPC processors. To satisfy the critics inside of IBM who complained that they were not full PowerPC processors, they were called PowerPC-AS processors. The AS supposedly was for Advanced Series, but most of us preferred to think it was for Amazon Series.

Meanwhile, the Belatrix project failed. The technology simply wasn't available in the middle 1990s to create a single-chip microprocessor that was equally at home in a technical computing environment and a commercial environment. As a result, IBM continued to develop the POWER architecture for use in the high-performance technical computing marketplace.

In Rochester, work was beginning on a new generation of microprocessors that would include the full PowerPC architecture. Because Belatrix was named after a star, and Minnesota is known as the Northstar state, the name Northstar was selected for the new processor. An entire family of microprocessors based on the Northstar design was being planned. The idea was to implement the same fundamental design in a new IBM semiconductor technology for each of four years. The result was the star family of microprocessors: Northstar, Pulsar, I-Star, and S-Star.

Even before the first member of the star family was ready to ship in a server, the Rochester engineers were able to build a microprocessor that incorporated the full PowerPC architecture. They essentially took the single-chip Cobra processor design (Muskie was a multichip design) and added the missing PowerPC features. One of these new features was a multiprocessor capability that was not available on Cobra. The result in 1997 of this effort was a new microprocessor for the AS/400 known as Apache.

Because Apache supported the full PowerPC architecture (32- and 64-bit versions), it could also be used in commercial models of the RS/6000. This was the first time the two server lines shared a common processor. The Apache microprocessor in the AS/400 was still called the PowerPC-AS, while in the RS/6000 the exact same Apache microprocessor was called the RS64-I. This was also the first 64-bit processor in the RS/6000 product line.

The following year, 1998, saw the introduction of Northstar, the first member of the star family of microprocessors, in both the AS/400 and the RS/6000. Again, in the AS/400, Northstar was called PowerPC-AS, while in the RS/6000 it was called RS64-II. The remaining members of the star family (Pulsar, I-Star, and S-Star) were introduced one at a time over the next three years.

A close look at the members of the star family shows that each microprocessor implements three complete processor architectures. These three architectures are: 64-bit Amazon, 64-bit PowerPC, and 32-bit PowerPC. These three architectures are closely related to one another. The 32-bit PowerPC architecture is a subset of 64-bit PowerPC, which in turn is a subset of 64-bit Amazon. Notice that there is no 32-bit Amazon. Amazon exists only as a 64-bit architecture.

To put some additional perspective on these relationships, the original 32-bit PowerPC architecture defined 187 instructions. The 64-bit PowerPC architecture added another 41 instructions for a total of 228 instructions. The original Amazon architecture added another 25 instructions to bring the total to 253 instructions. By the time hardware convergence between the AS/400 and RS/6000 had been achieved in 1997, the number of instructions in the Amazon architecture had grown to 385.

These numbers are continuously changing, because new instructions are added for each new processor implementation to support new functions. For example, new instructions were added over time to support Linux on the iSeries. Similarly, new instructions were added to the later processors in the star family to support partial processor LPAR functions. As a result, S-Star has more instructions than does Northstar. This also helps to explain why some new software functions run only on the newer microprocessors.

Different operating systems use different processor architectures. For example, OS/400 uses the Amazon architecture with the addressing structure that is designed to support single-level store. AIX originally used the 32-bit PowerPC architecture but now uses the 64-bit PowerPC architecture. Linux also originally used the 32-bit PowerPC architecture, but with the introduction of the 64-bit Linux kernel, it too can use the 64-bit PowerPC architecture.

Applications also use the different processor architectures. OS/400 applications use the 64-bit Amazon architecture. AIX and Linux applications use either 32- or 64-bit PowerPC, depending on the processor target when the application was compiled.

How does the processor know what architecture to use? Bit settings in the internal-processor control registers tell the hardware which architecture to use. These control bits are carried along with each process in the system and are loaded into the control registers when the process becomes active. Thus, the processor has the ability to switch architectures as it moves from executing one process to another. Depending on the bit settings in the control registers, the processor can interpret instructions that look very much alike differently.

This ability of processors to switch between architectures allowed the iSeries to easily implement an AIX runtime environment. Known as PASE for Portable Application Solutions Environment (a name that is about as ugly as IMPI), this capability allows an AIX application to run alongside an OS/400 application with the processor switching architectures as needed. This has proven to be so successful that PASE is now part of OS/400.

After the demise of Belatrix, IBM engineers from Rochester, Austin, and IBM Research began to look at new microprocessor designs that could support the full Amazon and the full POWER architectures in a single processor. In September 1996, the GigaProcessor program officially began. The goal of this program was not only to deliver a new high-performance microprocessor in 2001 that combined the Amazon and POWER architectures but also to provide two complete processors on a single chip.

In October 2001, the new microprocessor was introduced in the pSeries as the POWER4 processor. The following April, it was brought to the iSeries. While the star family was optimized for commercial applications, POWER4 was designed to address both commercial and technical computing requirements.

Like the star family of microprocessors, POWER4 supports multiple processor architectures. The star family supports three architectures; POWER4 supports five architectures: 64-bit Amazon, 64-bit PowerPC, 32-bit PowerPC, 64-bit POWER, and 32-bit POWER.

Advances in semiconductor technologies have made it possible to add new functions, and even whole new architectures, to our microprocessors. An ongoing question for processor designers is how to use all of the transistors that can be packaged on a single chip.

The POWER5 microprocessor is expected to appear in 2004. Like POWER4, it will have two processors per chip and will support the multiple architectures just discussed. In addition, it will support what IBM calls "Fast Path." POWER5 will be able to directly execute some common software tasks that are currently found in operating systems.

Instead of using a sequence of instructions to perform a common function, the operating system will use a single instruction that causes the entire function to be performed by the POWER5 microprocessor hardware. Examples of these common functions include TCP/IP processing, communications message-passing operations, and virtual memory subsystem operations, to name a few. The interfaces to all of these silicon accelerators will be open so that other operating systems, for example Linux, can take advantage of them.

Another new feature in POWER5 will be simultaneous multithreading (SMT). The idea behind SMT is to share the processor hardware on a chip among multiple threads in a multiprogrammed workload. In this way, a single processor on the chip can sometimes act as two processors.

The star family of microprocessors already supports a form of multithreading. Each star family chip contains two complete sets of processor registers to support two separate threads of execution. The processor executes instructions out of one set of registers until a cache miss occurs. Rather than waiting for the cache miss to finish, the processor switches to the second set of registers and begins to execute instructions from the second thread. This capability in the star family increases the performance by about 30 percent over a single processor's performance.

POWER4 did not implement multithreading because there were not enough transistors on a chip to build two full processors and all the hardware needed for multithreading. POWER5 has enough transistors to do both. The goal of the POWER5 is to achieve a 100 percent increase in processor performance using simultaneous multithreading. In other words, each processor on the POWER5 chip will behave like two processors running at full speed. Thus, each POWER5 chip will contain the equivalent of four complete processors.

When POWER6 arrives in 2006, it is expected to extend the Fast Path idea to even higher-level software such as DB2 and WebSphere processing. Again, all of the silicon accelerator interfaces will be open, so other software developers wil be able to take advantage of the improved performance.

The POWER4 microprocessor is the most sophisticated server processor on the market. POWER5 promises to extend that lead, and the development of POWER6 is well underway. Even though it is often convenient to call the processor architecture that these microprocessors support PowerPC, as we have just seen, they actually support multiple architectures. Future generations of POWER processors will likely support even more architectures. Sometimes PowerPC really isn't just PowerPC.

Frank G. Soltis of IBM Rochester created the technology-independent architecture used in the AS/400 and iSeries. He is IBM's iSeries chief scientist and a professor of computer engineering at the University of Minnesota.

Architectures Defined

When IBM introduced the System/360 architecture in 1964, it defined "architecture" as the interface to the machine, both hardware and microcode, as observable by the program. In general, this meant the instructions and the data types that the program could use. This definition was one of the first uses of the term "architecture" pertaining to a computer system.

Ever since that time, the term architecture has become more popular and has taken on a much broader meaning. Today, the term is used to describe both hardware and software interfaces. It is also used to describe system structures, that is, how various hardware and software components in a system fit together.

In order to keep all of these possible architecture definitions straight, we usually have to resort to some modifier to identify which architecture we are describing. Thus, in a hardware sense we have processor architectures, I/O architectures, and memory architectures. Both PowerPC and POWER are processor architectures. Software architecture definitions run the gamut from fairly low-level software interfaces (for example, "IP architecture") to the description of whole operating systems (for example, "Unix architecture"). In an even broader sense, when a business IT architecture is described, the definition usually means the system structure and how the various systems and applications fit together. "Data warehousing architecture" is a good example of this later type of definition. For the purposes of this article, we will stick to the discussion of processor architectures.

— F.G.S.

A Brief History of POWER and PowerPC

During the 1980s, IBM researchers created an enhancement to RISC processor designs that allowed the processor hardware to start the execution of multiple instructions in a single cycle. They called this enhancement superscalar. The first superscalar RISC processor appeared in the RS/6000 in 1990. To identify this superscalar enhancement to a RISC processor, IBM named the architecture POWER for Performance Optimization With Enhanced RISC. The POWER architecture was the starting point for the joint effort between Apple, IBM, and Motorola in 1991 to develop a new RISC processor architecture.

To meet the needs for all three corporations, certain modifications to the POWER architecture were required. Most of the early POWER processors were multichip implementations. The architecture had to be simplified somewhat to enable the building of low-cost, single-chip implementations. For future expansion, multiprocessing extensions were added and the 32-bit architecture was extended to include 64-bit addressing and operations. The changes resulted in the new PowerPC architecture.

Because many of the more complex floating-point instructions from the POWER architecture were not included in the PowerPC architecture, IBM continued to develop POWER processors for technical computing applications. The POWER2 processor was introduced in 1995. It featured a second floating-point pipeline, which greatly enhanced performance on technical workloads.

As the AIX operating system was being moved to the PowerPC architecture to run on a processor that was common between the AS/400 and RS/6000, it was apparent that the POWER architecture would have to become PowerPC compatible. Otherwise, two different versions of AIX would have to be maintained, and that wasn't desirable. Also, the POWER2 processors did not support multiprocessors, another feature that the PowerPC architecture had.

The first POWER3 processors debuted in early 1999. They were fully PowerPC compatible and supported multiprocessor configurations. Similar to Amazon, POWER3 implemented the full PowerPC architecture but also included many POWER instructions that were not in the PowerPC architecture.

The POWER4 processor was introduced in 2001. It was the first processor to support the Amazon, POWER, and PowerPC architectures. At last, IBM had a processor that fully supported both commercial and technical computing workloads.