|
Optimization Of Power For Sequential Elements In Pulse Triggered Flip-Flop Using Low Power Topologies
[Full Text]
AUTHOR(S)
Saranya. L, Prof. S. Arumugam
KEYWORDS
Keywords :- Flip-flop,ip-DCO,MHLFF,SCCER .
ABSTRACT
ABSTRACT : - The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. Here three kind of conventional pulse-triggered flip-flop are designed. First, the implicit Pulsed Data-Close to output (ip-DCO) pulse-triggered flip-flop. Second, the Modified Version of Hybrid latch flip-flop (MHLFF) and third is the Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop. These three flip-flops are studied and designed. The comparison of low power pulse triggered flip-flops between SAL ,SVL logics is carried out and the best power -delay-performance is obtained. The simulation results are obtained with Tanner simulation tool.
REFERENCES
[1]. H. Kawaguchi and T. Sakurai, “A reduced clock-swing flip-flop(RCSFF) for 63% power reduction,” IEEE J. Solid-State Circuits, vol.33, no. 5, pp. 807–811, May 1998.
[2]. A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, “A novel highspeed sense-amplifier-based flip-flop,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005.
[3]. H. Partovi, R. Burd, U. Salim, F.Weber, L. DiGregorio, and D. Draper,“Flow-through latch and edge-triggered flip-flop hybrid elements,” inIEEE Tech. Dig. ISSCC, 1996, pp. 138–139.
[4]. B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statisticalpower reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.1263–1271, Aug. 2001.
[5]. N. Nedovic, M. Aleksic, and V. G. Oklobdzija, “Conditional prechargetechniques for power-efficient dual-edge clocking,” in Proc. Int. Symp.Low-Power Electron. Design, Monterey, CA, Aug. 12–14, 2002, pp.56–59.
[6]. P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low power conditional discharge flip-flop,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 12, no. 5, pp. 477–484, May 2004.
[7]. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki,“Conditional data mapping flip-flops for low-power and high-performancesystems,” IEEE Trans. Very Large Scale Integr. (VLSI) Systems,vol. 14, pp. 1379–1383, Dec. 2006.
[8]. S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani,“Lowpower single- and double-edge-triggered flip-flops for high speedapplications,” Proc. Inst. Electr. Eng.—Circuits Devices Syst., vol. 152,no. 2, pp. 118–122, Apr. 2005.
[9]. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra lowpower clocking scheme using energy recovery and clock gating,” IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 17, pp. 33–44, Jan.2009.
[10]. P. Zhao, J. McNeely, W. Kaung, N. Wang, and Z. Wang, “Design osequential elements for low power clocking system,” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., to be published.
[11]. Y.-H. Shu, S. Tenqchen, M.-C. Sun, and W.-S. Feng, “XNOR-baseddouble-edge-triggered flip-flop for two-phase pipelines,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 53, no. 2, pp. 138–142, Feb. 2006.
[12]. M. Janaki Rani and S. Malarkann,” leakage power reduction and analysis of cmos sequential circuits” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012 DOI .
|
