HPCwire: MULTIPROG Issues Call for Papers

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July 25, 2012

MULTIPROG Issues Call for Papers

July 25 -- Computer manufacturers have already embarked on the multi-core roadmap, promising to add more and more cores/hardware threads on a chip: many-cores are on the horizon. This shift to an increasing number of cores and heterogeneous architectures has placed new burdens on the programming community. Until now, software has been developed with a single processor in mind and it needs to be parallelized and optimized for accelerators such as GPUs to take advantage of the new breed of multi-/many-core computers.

As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand. The sixth edition of the MULTIPROG workshop aims to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture, with special emphases on heterogeneous architectures.

A wide spectrum of issues are central themes for this workshop such as what the future programming models should look like to accelerate software productivity, how compilers, run-times and architectures should support these new programming models, innovative

algorithm and data structure development, and heterogeneous embedded, accelerated systems.

MULTIPROG is intended for quick publication of early results, work-in-progress, etc, and

is not intended to prevent later publication of extended papers.

We will prioritize papers addressing cross-cutting issues and that provide thought-provoking

insights into the main themes. Informal proceedings with accepted papers will be made available

at the workshop. One AMD Best Paper Award will be presented to the most outstanding paper

presented at MULTIPROG'13. The winner will receive a high-end ATi graphics card sponsored by AMD.

Topics of interest

Papers are sought on topics including, but not limited to:

* Multi-core architectures

o Architectural support for compilers/programming models

o Processor (core) architecture and accelerators, in particular GPUs

o Memory system architecture

o Performance, power, temperature, and reliability issues

* Heterogeneous computing

o Algorithms and data structures for heterogeneous systems

o Applications for heterogeneous computing and real-time graphics

* Programming models for multi-core architectures

o Language extensions

o Run-time systems

o Compiler optimizations and techniques

o Tools for discovering and understanding parallelism

* Benchmarking of multi-/many-core architectures

o Tools for understanding performance and debugging

o Case studies and performance evaluation

Organizers

Eduard Ayguade UPC and Barcelona Supercomputing Center, Spain (eduard@ac.upc.edu)

Benedict R. Gaster Advanced Micro Devices (AMD), USA (benedict.gaster@amd.com)

Lee Howes Advanced Micro Devices (AMD), USA (lee.howes@amd.com)

Per Stenstrom Chalmers University of Technology, Sweden (pers@chalmers.se)

Osman S. Unsal BSC-Microsoft Research Centre, Spain (osman.unsal@bsc.es)

Important dates

Abstract Submission: October 8, 2012

Final Submission: October 15, 2012

Author Notification: December 3, 2012

Paper submission

Submitted papers should use the LNCS format and should be 12 pages maximum. Manuscript

preparation guidelines can be found at the LNCS web site. Please check that (i) pages are

numbered, and (ii) graphs etc. remain legible when printed in black and white. Additional

information about paper submission will be available through the workshop website.

-----

Source: MULTIPROG

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