HPCwire: UK Lab Fires Up New GPU Cluster

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Translation Disclaimer

Subscribe | Sign In

Visit additional Tabor Communication Publications

Leading HPC
Solution Providers

July 03, 2012

UK Lab Fires Up New GPU Cluster

Robert Gelber

In the UK, a new HPC system at the Science and Technology Facilities Council’s (STFC) Rutherford Appleton Laboratory (RAL) is set to begin service today. The cluster named “Emerald” is the region’s fastest GPU-accelerated HPC machine. It will be accompanied by “Iridis 3,” which is hosted by the University of Southampton.

Together, both systems have been funded by a £3.7 million grant from the Engineering and Physical Sciences Research Council (EPSRC), which is part of a larger £145 million investment in e-infrastructure. David Willetts, Minister for Universities and Science, discussed the systems and their e-infrastructure funding in an official statement:

"These two new supercomputers form part of the Government's £145 million investment in e-infrastructure and will be invaluable assets to business and universities. They will drive growth and innovation, encourage inward investment in the UK and keep us at the very leading edge of science."

Researchers have already planned to use the systems for studies in astrophysics, healthcare, bioinformatics and simulations of communications technologies. Specific areas include, swine flu research, pulsar detection for the upcoming Square Kilometer Array, next-generation genome sequencing, and modeling cellular communications. Both clusters are set to provide substantial compute capacity for these workloads.

Emerald is an 84-node HP cluster outfitted with NVIDIA M2090 GPUs. All the nodes run twin 6-core, Xeon E5649 chips, but in two GPU configurations. Sixty of the nodes are equipped with three of the M2090s and 48 GB of main memory, while the remaining 24 units house eight GPUs and 96 GB of memory. The cluster is hooked together via QDR InfiniBand. Total performance amounts to 114.4 Linpack teraflops, which earned Emerald the number 159 spot on June’s TOP500 list.

Iridis has been active since 2010, when the supercomputer landed at number 74 on the TOP500. Powered by 12,000 Intel Xeon “Westmere” cores, the cluster, like Emerald, has two node configurations: standard compute units with 22 GB of memory, and high memory units with 45 GB. Peak performance is 72 teraflops.

The Emerald deployment coincides with the official launch of the e-Infrastructure South Consortium, which consists of the University College London, Bristol, Southampton and Oxford Universities. Together, the institutions have partnered with the Department of Scientific Computing at RAL to build the e-infrastructure South Centre for Innovation. The new center will play host to both systems.

Share Options

Subscribe

Subscribe to HPCwire

Discussion

There are 0 discussion items posted.

Join the Discussion

Become a Registered User Today!

Registered Users Log in join the Discussion

RSS Feeds

Feeds by Topic

Feeds by Industry

Feeds by Content Type

Subscribe to All Content

All

July 11, 2012

July 10, 2012

July 09, 2012

July 06, 2012

July 05, 2012

July 04, 2012

July 03, 2012

July 02, 2012

Feature Articles

Hybrid Memory Cube Angles for Exascale

Computer memory is currently undergoing something of an identity crisis. For the past 8 years, multicore microprocessors have been creating a performance discontinuity, the so-called memory wall. It's now fairly clear that this widening gap between compute and memory performance will not be solved with conventional DRAM products. But there is one technology under development that aims to close that gap, and its first use case will likely be in the ethereal realm of supercomputing.
Read more...

Green500 Turns Blue

The latest Green500 rankings were announced last week, revealing that top performance and power efficiency can indeed go hand in hand. According to the latest list, the greenest machines, in fact the top 20 systems, were all IBM Blue Gene/Q supercomputers. Blue Gene/Q, of course, is the platform that captured the number one spot on the latest TOP500 list, and is represented by four of the ten fastest supercomputers in the world.
Read more...

NERSC Signs Up for Multi-Petaflop "Cascade" Supercomputer

The US Department of Energy's National Energy Research Scientific Computing Center (NERSC) has ordered a two-petaflop "Cascade" supercomputer, Cray's next-generation HPC platform. The DOE is shelling out $40 million dollars for the system, including about 6.5 petabytes of the company's Sonexion storage. Installation is scheduled for sometime in 2013.
Read more...

Read more HPCwire features...

Tackling the Data Deluge: File Systems and Storage Technologies

06/25/2012 | NetApp | A single hour of data collection can result in 7+ million files from just one camera. Collection opportunities are limited and must be successful every time. As defense and intelligence agencies seek to use the data collected to make mission-critical battlefield decisions, there’s greater emphasis on smart data and imagery collection, capture, storage and analysis to drive real-time intelligence. The data gathered must accurately and systematically be analyzed, integrated and disseminated to those who need it – troops on the ground. This reality leads to an inevitable challenge – warfighters swimming in sensors, drowning in data. With the millions, if not billions, of sensors providing all-seeing reports of the combat environment, managing the overload demands a file system and storage infrastructure that scales and performs while protecting the data collected. Part II of our whitepaper series highlights NetApp’s scalable, modular, and flexible storage solution to handle the demanding requirements of sophisticated ISR environments.

View the White Paper Library

Michael Wolfe Webinar: PGI Accelerator with OpenACC

Join Michael for a look at the first PGI Accelerator Fortran and C compilers to include comprehensive support for OpenACC, the new open standard for programming accelerators using compiler directives.