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| | | | | | | | | | | | | | | | | | | | | | | | | | Packaging and Development |
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Nx586 Processor
Product Brief
Advanced Fifth Generation Technologies For 586-Class Performance
- Superscalar Execution
- On-chip separate L1 code and data caches
- Branch Prediction
- 64-bit buses
NexGen Advances and Benefits
RISC86 Microarchitecture
- Provides high performance and future extensibility
- On-chip L2 Cache Controller
Provides maximum performance and lower PC costs
Superscalar Execution
Previous generation x86 microprocessors furnish only one execution unit that processes instructions. The superscalar Nx586 and Pentium processors both have two integer execution units which allow for higher performance computing. The Nx586 processor's RISC86 microarchitecture provides a very efficient implementation for high performance and future extensibility.
Harvard Architecture L1 Cache Design
An additional major 586-class performance improvement comes from using separate Harvard Architecture on-chip code and data caches for the level-one cache memory. To take best advantage of the level-one cache, the Nx586 processor includes separate 16-Kbyte instruction and 16-Kbyte data caches compared to 8K each for the Pentium. These caches keep key instruction and data close to the processing engines to increase overall system performance.
Branch Prediction
If the processor can predict the branch ("decision") an application will take, processing can immediately proceed if that decision becomes valid. 586-class processors thus include branch prediction circuitry. The Nx586 processor's patented branch prediction logic accurately predicts these branches in the vast majority of cases, thus enhancing performance.
64-bit buses
586-class processors employ 64-bit buses -- twice the size of the buses in previous generation processors. The larger buses move data faster and therefore improve performance. The Nx586 processor employs 64-bit buses within the system including those between Nx586 processor and the Nx587 coprocessor, and between the Nx586 processor and the NxVL or NxPCI system logic chipset.
RISC86 Microarchitecture
The Nx586 processor fully implements the industry standard x86 instruction set to be able to run the more than 50,000 applications now available. This implementation is accomplished through the use of NexGen's patented RISC86 microarchitecture. The innovative RISC86 approach dynamically translates x86 instructions into RISC86 instructions. These RISC86 instructions were specifically designed with direct support for the x86 architecture while obeying RISC performance principles. They are thus simpler and easier to execute than the complex x86 instructions. Note that this approach is fundamentally different than RISC processors, which have no support whatsoever for the x86 instruction set architecture. The RISC86 microarchitecture also contains many state-of-the-art computer science techniques to achieve very high performance, including register renaming, data forwarding, speculative execution, and out-of-order execution.
The benefits of this approach are several. First, the performance advantages of RISC design are applied to the x86 instruction set. Second, the execution unit can be smaller and more compact. Third, the execution units can be more specialized to give specific performance enhancements. Finally, it will be easier to add additional execution units in future designs. The RISC86 microarchitecture not only gives the Nx586 processor high performance today, but also allows for significantly higher performance in the future.
On-chip L2 Cache Controller
Unlike the Pentium processor, the Nx586 processor incorporates its own level two cache controller directly on-chip. This assures the level-two cache will always run at full performance today as well as in future higher-clock-rate Nx586 processors. The on-chip second-level cache controller also lowers PC costs because it allows the Nx586 processors to run at full speed with slower - and less expensive - cache memory.
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